The present invention relates to a USB (Universal Serial Bus) device, and more particularly to a USB 3.0 device.
USB 3.0 that provides backward compatibility with USB 2.0 includes SuperSpeed (SS) enabling superspeed transmission at 5 Gbps in addition to low-speed (LS), full-speed (FS), and high-speed (HS) in USB 2.0.
In order to realize SS communication, various ideas are incorporated in USB 3.0. For example, since attenuation in UTP (Unshielded Twist Pair) cables that are used in USB 2.0 is too high for SS communication, USB 3.0 further includes two pairs of SDP (Shielded Differential Pair) cables as communication lines supporting SS in addition to the UTP cables complying with the USB 2.0 for USB 2.0 communication.
Moreover, as shown in FIG. 17 (FIG. 10-3 in Universal Serial Bus 3.0 Specification Revision 1.0 (Nov. 12, 2008)), the circuit blocks of USB 3.0 apparatuses (host, hub, and device) further include blocks for SS (SuperSpeed portions) separately from blocks of USB 2.0 (Non-SuperSpeed portions). Note that in the explanation of this specification, the “USB apparatus” indicates both a USB host and a USB device, and also includes a USB hub. The USB hub has a function of both USB host and USB device, being the USB device for the USB host and the USB host for the USB device.
SS USB 3.0 having a different physical layer from USB 2.0 inherits many parts of a higher protocol layer from USB 2.0 in order to fully utilize the resources of USB 2.0 and uses existing class drivers in an application layer. In order to resolve a gap between the physical layer that is different from USB 2.0 and the protocol layer with no significant change from USB 2.0, USB 3.0 further includes a link layer in charge of packet framing, link establishment, and power management.
FIG. 18 is a hierarchical model diagram of a USB 3.0 apparatus. As shown in FIG. 18, a USB 3.0 apparatus 10 includes an SS portion 30 that is added in USB 3.0, a USB 2.0 portion 40, and a common portion 20 that is commonly used by the SS portion 30 and the USB 2.0 portion 40. The USB 2.0 portion 40 includes a USB 2.0 endpoint controller 42, a UTMI (USB 2.0 Transceiver Macrocell Interface) 44, and an HS/FS/LS physical layer 46. The SS portion 30 includes an HS/FS/LS endpoint controller 32, a link layer 34, and an SS physical layer 36. Note that USB 3.0 specifies provision of support for at least one of LS, FS, and HS in USB 3.0 and do not allow support for only SS and not supporting any of LS/FS/HS.
The link layer 34 in FIG. 18 is added to realize SS in USB 3.0. Some states are defined in the link layer of SS and transition conditions of the states are specified. Relevant parts to the present invention are explained with reference to FIG. 19.
FIG. 19 is FIG. 7-13 in Universal Serial Bus 3.0 Specification Revision 1.0 (Nov. 12, 2008), and indicates LTSSM (Link Training and Status State Machine) state transitions in USB 3.0.
An Rx.Detect state in FIG. 19 is a state to detect the presence of a link partner. In the Rx.Detect state, the USB 3.0 apparatus performs a process called “Receiver Detection”, and detects presence of a teimination resistance called “Rx.Termination” in transceiver lines for SS. The mechanism of the Receiver Detection is explained with reference to FIGS. 20 and 21.
FIGS. 20 and 21 respectively illustrate cases where the abovementioned termination resistance (i.e., Rx.Termination, which is R_Term 60 in the drawing) is not present in the transceiver lines for SS and the case where the termination resistance is present in the transceiver lines for SS.
A transmission unit in a USB 3.0 apparatus which performs the Receiver Detection is an SS transmission line for the USB 3.0 apparatus and turns on a switch provided on a communication line, which is an SS reception line for a destination USB 3.0, in order to apply voltage (SW control voltage in the drawings) to the communication line. A reception unit is an SS reception line for the source USB 3.0 and connects the R_Term 60 provided on a communication line, which is an SS transmission line for the destination USB 3.0 apparatus.
After the switch 50 turns on, the source USB 3.0 apparatus monitors changes in voltage (V_Detect) of the SS transmission line and detects the presence of the R_Term 60 from the changes in the V_Detect. Below is an explanation with reference to FIG. 22.
The SW control voltage applied to the SS transmission line during the Receiver Detection is shown in the upper part of FIG. 22. When the destination USB apparatus supports SS and is in the Rx.Detect state (the state shown in FIG. 21, i.e., the R_Term 60 is connected), the V_Detect gradually increases as indicated by a curved line C2 in the drawing. On the other hand, when the destination USB apparatus does not support SS or support SS but the R_Term 60 is not connected (the state shown in FIG. 20), the V_Detect rapidly increases as indicated by a curved line C1 in the drawing.
The source USB 3.0 apparatus samples the V_Detect with threshold voltage called Vthreshold and detect the presence of the R_Term 60 from the sampled result. Note that USB 3.0 specifies that this detection is performed up to eight times.
Turning back to FIG. 19, the explanation will be continued further. In the Rx.Detect state, when the R_Term 60 is detected within eight times, LTSSM will transition to a Polling state. The operations so far are same whether the source USB 3.0 apparatus is a USB 3.0 host or a USB 3.0 device.
In the Rx.Detect state, when the R_Term 60 is not detected within eight times of detection, the subsequent operations are different for the USB 3.0 host and the USB 3.0 device.
When the source USB 3.0 apparatus is the USB 3.0 host, the host returns to the Rx.Detect state upon an instruction to resume the Receiver Detection from an upper layer (driver and the like) of the link layer. When there is no resume instruction from the upper layer, upon detection of pull-up of D+ or D−, the host performs USB 2.0 Bus Reset (hereinafter may be also referred to as merely “Bus Reset”), attempts a USB 2.0 connection with the destination (device), and further detects the R_Term 60. Although USB 3.0 does not limit the number of executing Bus Reset by the host, USB 3.0 specifies that detection of the R_Term 60, i.e., the Receiver Detection is performed only once per Bus Reset. When the R_Term 60 is detected in one Receiver Detection, LTSSM transitions to the Polling state and the link procedure in SS is performed. On the other hand, when the R_Term 60 is not detected in this detection, the host continues the USB 2.0 connection with the destination.
When the source is the USB 3.0 device and the R_Term 60 is not detected within eight times of detection, the device enters an SS.Disabled state.
As shown in FIG. 19, the USB 3.0 device in the SS.Disabled state will not return to the Rx.Detect state without PowerOn Reset or the USB 2.0 Bus Reset.
When the USB 3.0 device enters the SS.Disabled state, the USB 3.0 activates the USB 2.0 portion 40 (see FIG. 18) in the USB 3.0 device and is prepared for a USB 2.0 connection with the destination (host in this example). In parallel with this, upon the USB 2.0 Bus Reset by the USB 3.0 host, the USB 3.0 device returns to the Rx.Detect state and performs the Receiver Detection again. USB 3.0 specifies that also for the device, the Receiver Detection here is performed only once per Bus Reset. When the R_Term 60 is detected by this Receiver Detection, the USB 3.0 device transitions to the Polling state and will perform the link procedure in SS.
In the following explanation, only one Receiver Detection along with Bus Reset shall be referred to as “Bus Reset Receiver Detection” for the sake of convenience.